In many computer applications, synchronously operating computing system components communicate with each other over a synchronous bus. Signals transmitted between these components include both command and data information.
When a synchronous bus is used to couple a number of synchronously operating computing system components, clocking signals are distributed to each component over the bus. These clocking signals may be generated at a central location and then provided to each component connected to the bus. This type of radially distributed clock scheme is common in computer systems.
Generally, the clocking signals are generated at a central source, such as a bus clock module or utility module. The signals that are generated by the source are usually digital, positive emitter coupled logic (PECL), or emitter coupled logic (ECL) signals.
Each component that is connected to the synchronous bus buffers the clocking signal with a repeater or level converter or other device that carries out the equivalent processing function. Due to the different distances that the clocking signals travel to reach the repeater or level converter at the components, the clocking signals are skewed. Normally, the repeater uses phase locked loop (PLL) or digital locked loop (DLL) techniques to minimize skewing that occurs. When the system can tolerate a greater amount of clock skew, a simple one-to-eight fanout buffer chip may be used. Besides the distance problem, temperature, semiconductor and module processing, voltage levels, load, and other variations are factors which also may affect clocking skew.
There is a need for a clock distribution scheme which reduces clocking skew in components of a computing system connected to a synchronous bus without the need to use digital or phase lock loop devices to avoid jitter and locking problems.